Techniques for Enabling Multiple Vt Devices Using High-K Metal Gate Stacks

ABSTRACT

Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.12/720,354 filed on Mar. 9, 2010, the contents of which are incorporatedby reference herein.

FIELD OF THE INVENTION

The present invention relates to integrated circuits, and moreparticularly, to techniques for combining transistors in an integratedcircuit having different threshold voltage requirements from oneanother.

BACKGROUND OF THE INVENTION

Integrated circuits now commonly include a wide variety of differenttransistor types in combination with one another. By way of example,random access memory transistors, such as static random access memory(SRAM) or dynamic random access memory (DRAM) transistors, are in manyconfigurations used in combination with a variety of logic transistors.A challenge, however, associated with integrating different transistorsis that each type of transistor generally requires a threshold voltage(V_(t)) that is different from what the other types of transistorsrequire. For example, with integrated circuit configurations thatcombine SRAM and logic transistors, the SRAM transistors typicallyrequire a higher V_(t) than their logic counterparts. This V_(t)difference is due to the relatively lower power requirements of SRAMtransistors, i.e., as compared to logic transistors.

In conventional designs, these different V_(t) requirements areaddressed through doping. Specifically, extra doping steps are performedto alter the V_(t) of the SRAM transistors relative to the logictransistors, and vice versa. This approach, however, has a notabledrawback. Since the V_(t) of the transistors is determined throughdoping, the doping must be consistent from one device to another toattain consistent V_(t). Namely, dopant fluctuations, which can occur ina significant number of devices produced, leads to variability in thetransistors. Variability in the transistors leads to variability in thedevices and thus affects device performance. As device feature sizes arescaled, the effects of dopant fluctuations and device variability becomeeven more pronounced.

Therefore, improved techniques for combining transistors havingdifferent V_(t) requirements would be desirable.

SUMMARY OF THE INVENTION

The present invention provides techniques for combining transistorshaving different threshold voltage (V_(t)) requirements from oneanother. In one aspect of the invention, a semiconductor device isprovided. The semiconductor device comprises a substrate having at leasta first and a second n-channel field effect transistor (nFET) region,and at least a first and a second p-channel field effect transistor(pFET) region; at least one logic nFET on the substrate over the firstnFET region; at least one logic pFET on the substrate over the firstpFET region; at least one static random access memory (SRAM) nFET on thesubstrate over the second nFET region; and at least one SRAM pFET on thesubstrate over the second pFET region. Each of the logic nFET, logicpFET, SRAM nFET and SRAM pFET comprises a gate stack having a metallayer over a high-K layer. The logic nFET gate stack further comprises acapping layer separating the metal layer from the high-K layer, whereinthe capping layer is further configured to shift a V_(t) of the logicnFET relative to a V_(t) of one or more of the logic pFET, SRAM nFET andSRAM pFET.

In another aspect of the invention, a method of fabricating asemiconductor device is provided. The method comprises the followingsteps. A substrate is provided having at least one logic nFET region, atleast one SRAM nFET region, at least one logic pFET region and at leastone SRAM pFET region. Crystalline silicon germanium is selectivelyformed in the logic pFET region. An interfacial layer dielectric isgrown over the logic nFET region, the SRAM nFET region, the logic pFETregion and the SRAM pFET region. A high-K layer is deposited over theinterfacial layer dielectric. A capping layer is formed in the logicnFET region over a side of the high-K layer opposite the interfaciallayer dielectric. A metal layer is deposited over the capping layer inthe logic nFET region and over the high-K layer in the SRAM nFET region,the logic pFET region and the SRAM pFET region. A silicon layer isdeposited over the metal layer. An etch is performed through theinterfacial layer dielectric, the high-K layer, the capping layer, themetal layer and the silicon layer to form a logic nFET gate stack overthe logic nFET region, and through the interfacial layer dielectric, thehigh-K layer, the metal layer and the silicon layer to form a SRAM nFETgate stack over the SRAM nFET region, a logic pFET gate stack over thelogic pFET region and a SRAM pFET gate stack over the SRAM pFET region.

In yet another aspect of the invention, another method of fabricating asemiconductor device is provided. The method comprises the followingsteps. A substrate is provided having at least one logic nFET region, atleast one SRAM nFET region, at least one logic pFET region and at leastone SRAM pFET region. An interfacial layer dielectric is grown over thelogic nFET region, the SRAM nFET region, the logic pFET region and theSRAM pFET region. A high-K layer is deposited over the interfacial layerdielectric. A capping layer is formed in the logic nFET region and theSRAM pFET region over a side of the high-K layer opposite theinterfacial layer dielectric. A metal layer is deposited over thecapping layer in the logic nFET region and the SRAM pFET region and overthe high-K layer in the SRAM nFET region and the logic pFET region. Asilicon layer is deposited over the metal layer. An etch is performedthrough the interfacial layer dielectric, the high-K layer, the cappinglayer, the metal layer and the silicon layer to form a logic nFET gatestack over the logic nFET region and a SRAM pFET gate stack over theSRAM pFET region, and through the interfacial layer dielectric, thehigh-K layer, the metal layer and the silicon layer to form a SRAM nFETgate stack over the SRAM nFET region and a logic pFET gate stack overthe logic pFET region.

The method can further comprise the following steps. A tensile siliconnitride layer is deposited over the logic nFET region and the SRAM nFETregion. The logic pFET region and the SRAM pFET region are oxidized. Acompressive silicon nitride layer is deposited over the logic pFETregion and the SRAM pFET region.

A more complete understanding of the present invention, as well asfurther features and advantages of the present invention, will beobtained by reference to the following detailed description anddrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-G are cross-sectional diagrams illustrating an exemplarymethodology for forming an integrated static random access memory(SRAM)-logic semiconductor device according to an embodiment of thepresent invention;

FIGS. 2A-G are cross-sectional diagrams illustrating another exemplarymethodology for forming an integrated SRAM-logic semiconductor deviceaccording to an embodiment of the present invention;

FIGS. 3A-G are cross-sectional diagrams illustrating yet anotherexemplary methodology for forming an integrated SRAM-logic semiconductordevice according to an embodiment of the present invention;

FIGS. 4A-L are cross-sectional diagrams illustrating still yet anotherexemplary methodology for forming an integrated SRAM-logic semiconductordevice according to an embodiment of the present invention; and

FIG. 5 is a graph illustrating a flat band voltage (V_(fb)) shift in ann-channel metal-oxide semiconductor capacitor (nMOSCAP) having ahigh-K/metal gate stack with a capping layer according to an embodimentof the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIGS. 1A-G are cross-sectional diagrams illustrating an exemplarymethodology for forming an integrated static random access memory(SRAM)-logic semiconductor device. The device can comprise, for example,an integrated circuit having a plurality of SRAM and logic transistors.

With integrated SRAM-logic devices, it is desirable to be able toaccurately and consistently alter the threshold voltage (V_(t)) of theSRAM transistors as compared to the V_(t) of the logic transistors. Forexample, the SRAM transistors will likely require a higher V_(t) thanthe logic transistors. As will be described in detail below, the presenttechniques involve transistors having high-K/metal gate stacks. Acapping layer can be selectively employed in one or more of the gatestacks and/or crystalline silicon-germanium (cSiGe) can be selectivelygrown to alter the V_(t) of the corresponding transistor(s).

As shown in FIG. 1A, a substrate 104 is provided. Substrate 104 cancomprise a silicon-on-insulator (SOI) substrate or a bulk silicon (Si)substrate. According to an exemplary embodiment, substrate 104 comprisesa SOI substrate having a Si layer over an insulator (such as silicondioxide (SiO₂)), wherein the Si layer has a thickness of between aboutfive nanometers (nm) and about 100 nm.

Substrate 104 has both SRAM and logic n-channel field effect transistor(nFET) and p-channel field effect transistor (pFET) regions definedtherein. Specifically, according to the exemplary embodiment shownillustrated in FIG. 1A, substrate 104 comprises logic nFET region 106,SRAM nFET region 108, logic pFET region 110 and SRAM pFET region 112.Each of logic nFET region 106 and SRAM nFET region 108 comprises Si andis doped with a p-type dopant. Each of logic pFET region 110 and SRAMpFET region 112 also comprises Si and is doped with an n-type dopant. Aswill be described below, cSiGe will be formed in each of logic pFETregion 110 and SRAM pFET region 112. The cSiGe in SRAM pFET region 112will have a reduced germanium (Ge) fraction. By way of example only, thecSiGe in SRAM pFET region 112 can have a Ge fraction of less than about30 percent (%), preferably between about 15% and about 25%. Bycomparison, the cSiGe in logic PFET region 110 can have a Ge fraction ofbetween about 30% and about 40%. The process for tuning the amount ofGe, i.e., during growth of the cSiGe, is known to those of skill in theart, and as such is not described further herein.

A hardmask layer is deposited over the device and patterned to formhardmask 114 over the nFET regions, i.e., over nFET region 106 and SRAMnFET region 108. With hardmask 114 shielding logic nFET region 106 andSRAM nFET region 108, cSiGe 113 and 115 are then selectively formed,i.e., grown, in logic pFET region 110 and SRAM pFET region 112,respectively. As described above, SRAM pFET region 112 has a reduced Gefraction, e.g., as compared to logic pFET region 110. According to anexemplary embodiment, this variation between the two pFET regions isaccomplished using a two-step masking process wherein a mask (not shown)is first placed over logic pFET region 110 and the cSiGe is formed inSRAM pFET region 112 having a reduced Ge fraction. The mask is removedand a second mask (not shown) is placed over SRAM pFET region 112 andthe cSiGe is formed in logic pFET region 110. The second mask is thenremoved. This two-step masking process is performed with hardmask 114 inplace. The sequence of this two-step masking process is not important,and can be performed wherein the cSiGe is first formed in logic pFETregion 110, followed by the cSiGe having the reduced Ge fraction beingformed in the SRAM pFET region 112.

As shown in FIG. 1B, hardmask 114 is stripped. According to an exemplaryembodiment, hardmask 114 is stripped using a wet chemical etch.

As shown in FIG. 1C, interfacial layer (IL) dielectric 116 is grown overthe nFET/pFET regions. According to an exemplary embodiment, ILdielectric 116 comprises SiO₂. Nitrogen is then incorporated (e.g., bynitridation, thermal nitridation and/or plasma oxidation followed bynitridation) into IL dielectric 116. High-K layer 118 is then depositedover a side of IL dielectric 116 opposite the nFET/pFET regions.According to an exemplary embodiment, high-K layer 118 comprises one ormore of hafnium oxide (HfO₂), zirconium oxide (ZrO₂), hafnium silicate(HfSiO), nitrided hafnium silicate (HfSiON), tantalum oxide (Ta₂O₅),titanium oxide (TiO₂), aluminum oxide (Al₂O₃) and mixtures comprising atleast one of the foregoing high-K materials.

Capping layer 120 is deposited over a side of high-K layer 118 oppositeIL dielectric 116. According to an exemplary embodiment, capping layer120 comprises one or more of lanthanum oxide (La₂O₃), magnesium oxide(MgO), oxides of group IIA and group IIIB elements and nitrides of groupIIA and group IIIB elements. Capping layers are described, for example,in U.S. Patent Application No. 2006/0289948 filed by Brown et al.,entitled “Method to control flatband/threshold voltage in high-k metalgated stacks and structures thereof” and in U.S. Patent Application No.2006/0244035 filed by Bojarczuk et al., entitled “Stabilization offlatband voltages and threshold voltages in hafnium oxide based silicontransistors for CMOS,” the disclosures both of which are incorporated byreference herein. As will be described below, in the completed device,capping layer 120 can provide between about a 300 millivolt (mV) andabout a 350 mV V_(t) shift in the nFET. Further, reduced Ge fractioncSiGe can provide between about a 200 mV and about a 350 mV V_(t) shiftin the pFET.

As shown in FIG. 1D, photoresist 124 is patterned over logic nFET region106. With photoresist 124 as a mask, capping layer 120 is selectivelyremoved, i.e., stripped, from over SRAM nFET region 108, logic pFETregion 110 and SRAM pFET region 112. According to an exemplaryembodiment, capping layer 120 is selectively removed from over SRAM nFETregion 108, logic pFET region 110 and SRAM pFET region 112 usinghydrochloric acid (HCl). For example, if high-K layer 118 comprises HfO₂(as described above) and if capping layer 120 comprises La₂O₃ (asdescribed above), HCl would be selective for the removal of the La₂O₃layer from the HfO₂ layer. For different capping layer compositions,other suitable chemistries can be used for selectively removing thecapping layer.

As shown in FIG. 1E, photoresist 124 is removed revealing the remainingportion of the capping layer formed over the logic nFET region, i.e.,capping layer 121 over logic nFET region 106. As shown in FIG. 1F, metallayer 126 is deposited over capping layer 121/high-K layer 118.According to an exemplary embodiment, metal layer 126 comprises one ormore of titanium nitride (TiN), tantalum nitride (TaN), tantalumaluminum nitride (TaAlN), titanium aluminum nitride (TiAlN), andtantalum carbide (TaC or Ta₂C).

A Si layer 128 is then deposited over a side of metal layer 126 oppositecapping layer 121/high-K layer 118. According to an exemplaryembodiment, Si layer 128 comprises polysilicon (poly-Si) and/oramorphous Si and is deposited to a thickness of about 1,000 angstroms(Å) at its thickest point. However, depending on the technology, thethickness of Si layer 128 can vary from between about 500 Å to about1,000 Å at its thickest point.

As shown in FIG. 1G, reactive ion etching (RIE) is then performedthrough the various layers to define individual gate stacks over each ofthe nFET and pFET regions. Namely, gate stack 130 is defined over logicnFET region 106. Gate stack 130 comprises IL dielectric 116 a (formedfrom IL dielectric 116), high-K layer 118 a (formed from high-K layer118) over IL dielectric 116 a, capping layer 121 a (formed from cappinglayer 121) over a side of high-K layer 118 a opposite IL dielectric 116a, metal layer 126 a (formed from metal layer 126) over a side ofcapping layer 121 a opposite high-K layer 118 a and Si layer 128 a(formed from Si layer 128) over a side of metal layer 126 a oppositecapping layer 121 a.

Gate stack 132 is defined over SRAM nFET region 108. Gate stack 132comprises IL dielectric 116 b (formed from IL dielectric 116), high-Klayer 118 b (formed from high-K layer 118) over IL dielectric 116 b,metal layer 126 b (formed from metal layer 126) over a side of high-Klayer 118 b opposite IL dielectric 116 b and Si layer 128 b (formed fromSi layer 128) over a side of metal layer 126 b opposite high-K layer 118b.

Gate stack 134 is defined over logic pFET region 110. Gate stack 134comprises IL dielectric 116 c (formed from IL dielectric 116), high-Klayer 118 c (formed from high-K layer 118) over IL dielectric 116 c,metal layer 126 c (formed from metal layer 126) over a side of high-Klayer 118 c opposite IL dielectric 116 c and Si layer 128 c (formed fromSi layer 128) over a side of metal layer 126 c opposite high-K layer 118c.

Gate stack 136 is defined over SRAM pFET region 112. Gate stack 136comprises IL dielectric 116 d (formed from IL dielectric 116), high-Klayer 118 d (formed from high-K layer 118) over IL dielectric 116 d,metal layer 126 d (formed from metal layer 126) over a side of high-Klayer 118 d opposite IL dielectric 116 d and Si layer 128 d (formed fromSi layer 128) over a side of metal layer 126 d opposite high-K layer 118d.

Standard processes can then be carried out to form source and drainregions on opposite sides of the gate stacks. Oxide and/or nitridespacers can also be formed around the gate stack, as needed.

As a result of performing the steps shown illustrated in FIGS. 1A-G, anddescribed above, the capping layer will be present only in gate stack130. As such, the corresponding logic nFET will have a V_(t) at bandedge. The capping layer shifts the logic nFET V_(t) by a combination ofdifferent processes. By way of example only, a) negative shifts in theV_(t) may be due to positively charged mobile oxygen vacancies that formupon the aliovalent substitution of Hf4+ in HfO₂ with lower valencelanthanum cation (La3+) or magnesium cation (Mg2+) and are needed tocompensate the negative effective charge of lanthanum hafnium (LaHf); b)the presence of a more electropositive impurity like lanthanum (La) ormagnesium (Mg) in the HfO₂ could result in a dipole, which would shiftthe V_(t) more negative (such a dipole would form as long as there is anon-symmetrical distribution in the La composition across the gatestack); and c) the interaction of La or Mg with the IL dielectric (e.g.,SiO₂) can result in negative V_(t) shifts by a combination of mechanismsa) and b).

By comparison, the SRAM nFET, which does not have a capping layer in itsgate stack, i.e., gate stack 132, will have a V_(t) that is about 200 mVgreater than the V_(t) of the logic nFET. For the pFETs, which also donot have a capping layer in their gate stacks, the V_(t) is on target(i.e., at or near pFET band edge). Further, the presence of reduced Gefraction cSiGe in the SRAM pFET (as described above) will provide apositive V_(t) shift of between about a 200 mV and about a 350 mV in theSRAM pFET, as compared to the V_(t) of the logic pFET. Thus, the use ofreduced Ge fraction cSiGe to shift V_(t) operates independently of theuse of a capping layer to shift V_(t). In general, the use of reduced Gefraction cSiGe provides a positive V_(t) shift, and the use of a cappinglayer provides a negative V_(t) shift.

The above-described techniques are beneficial since they minimize thenumber of masking steps involved, which is favorable for reducingproduction time and costs. Other techniques, however, may be employed.For example, the same gate stack configurations can be obtained using adifferent masking process. Specifically, with reference to the stepshown in FIG. 1C, a metal layer, e.g., a TiN layer, rather than thecapping layer, is deposited over the high-k layer. A mask is thenpatterned to cover the metal layer over the SRAM nFET, logic pFET andSRAM pFET regions, allowing for the selective removal of the metal layerfrom over the logic nFET region. Following the removal of the metallayer from over the logic nFET region, the mask is also removed.

A capping layer is then deposited over the metal layer/high-K layer,followed by a second metal layer, e.g., a second TiN layer, beingdeposited over the capping layer. A second mask is then patterned tocover the second TiN layer over the logic nFET region, allowing for theselective removal of the second TiN and capping layers from over theSRAM nFET, logic pFET and SRAM pFET regions. Following the removal ofthe second TiN and capping layers from over the SRAM nFET, logic pFETand SRAM pFET regions, the mask is also removed. From this point on, theremainder of the process is the same as is illustrated in FIGS. 1F-G(described above).

FIGS. 2A-G are cross-sectional diagrams illustrating another exemplarymethodology for forming an integrated SRAM-logic semiconductor device.The device can comprise, for example, an integrated circuit having aplurality of SRAM and logic transistors. As shown in FIG. 2A, asubstrate 204 is provided. Substrate 204 can comprise a SOI substrate ora bulk Si substrate. According to an exemplary embodiment, substrate 204comprises a SOI substrate having a Si layer over an insulator (such asSiO₂), wherein the Si layer has a thickness of between about five nm andabout 100 nm.

Substrate 204 has both SRAM and logic nFET and pFET regions definedtherein. Specifically, according to the exemplary embodiment shownillustrated in FIG. 2A, substrate 204 comprises logic nFET region 206,SRAM nFET region 208, logic pFET region 210 and SRAM pFET region 212.Each of logic nFET region 206 and SRAM nFET region 208 comprises Si andis doped with a p-type dopant. Each of logic pFET region 210 and SRAMpFET region 212 also comprises Si and is doped with an n-type dopant. Aswill be described below, cSiGe will be formed in each of logic pFETregion 210 and SRAM pFET region 212.

A hardmask layer is deposited over the device and patterned to formhardmask 214 over the nFET regions, i.e., over logic nFET region 206 andSRAM nFET region 208. With hardmask 214 shielding logic nFET region 206and SRAM nFET region 208, cSiGe 213 and 215 are then selectively formed,i.e., grown, in logic pFET region 210 and SRAM pFET region 212,respectively. As shown in FIG. 2B, hardmask 214 is stripped. Accordingto an exemplary embodiment, hardmask 214 is stripped using a wetchemical etch.

As shown in FIG. 2C, IL dielectric 216 is grown over the nFET/pFETregions. According to an exemplary embodiment, IL dielectric 216comprises SiO₂. Nitrogen is then incorporated (e.g., by nitridation,thermal nitridation and/or plasma oxidation followed by nitridation)into IL dielectric 216. High-K layer 218 is then deposited over a sideof IL dielectric 216 opposite the nFET/pFET regions. According to anexemplary embodiment, high-K layer 218 comprises one or more of HfO₂,ZrO₂, HfSiO, HfSiON, Ta₂O₅, TiO₂, Al₂O₃ and mixtures comprising at leastone of the foregoing high-K materials. Capping layer 220 is depositedover a side of high-K layer 218 opposite IL dielectric 216. According toan exemplary embodiment, capping layer 220 comprises one or more ofLa₂O₃, MgO, oxides of group IIA and group IIIB elements and nitrides ofgroup IIA and group IIIB elements.

As shown in FIG. 2D, photoresist 224 and 225 are patterned over logicnFET region 206 and SRAM pFET region 212. With photoresist 224 and 225as masks, capping layer 220 is selectively removed, i.e., stripped, fromover SRAM nFET region 208 and logic pFET region 210. According to anexemplary embodiment, capping layer 220 is selectively removed from overSRAM nFET region 208 and logic pFET region 210 using HCl.

As shown in FIG. 2E, photoresist 224 and 225 are removed, revealing theremaining portions of the capping layer formed over the logic nFET andthe SRAM pFET regions, i.e., capping layers 221 and 222 over logic nFETregion 206 and SRAM pFET region 212, respectively. As shown in FIG. 2F,metal layer 226 is deposited over high-K layer 218/capping layer221/capping layer 222. According to an exemplary embodiment, metal layer226 comprises one or more of TiN, TaN, TaAlN, TiAlN, TaC and Ta₂C.

A Si layer 228 is then deposited over a side of metal layer 226 oppositehigh-K layer 218/capping layer 221/capping layer 222. According to anexemplary embodiment, Si layer 228 comprises poly-Si and/or amorphous Siand is deposited to a thickness of about 1,000 Å at its thickest point.However, depending on the technology, the thickness of Si layer 228 canvary from about 500 Å to about 1,000 Å at its thickest point.

As shown in FIG. 2G, RIE is then performed through the various layers todefine individual gate stacks over each of the nFET and pFET regions.Namely, gate stack 230 is defined over logic nFET region 206. Gate stack230 comprises IL dielectric 216 a (formed from IL dielectric 216),high-K layer 218 a (formed from high-K layer 218) over IL dielectric 216a, capping layer 221 a (formed from capping layer 221) over a side ofhigh-K layer 218 a opposite IL dielectric 216 a, metal layer 226 a(formed from metal layer 226) over a side of capping layer 221 aopposite high-K layer 218 a and Si layer 228 a (formed from Si layer228) over a side of metal layer 226 a opposite capping layer 221 a.

Gate stack 232 is defined over SRAM nFET region 208. Gate stack 232comprises IL dielectric 216 b (formed from IL dielectric 216), high-Klayer 218 b (formed from high-K layer 218) over IL dielectric 216 b,metal layer 226 b (formed from metal layer 226) over a side of high-Klayer 218 b opposite IL dielectric 216 b and Si layer 228 b (formed fromSi layer 228) over a side of metal layer 226 b opposite high-K layer 218b.

Gate stack 234 is defined over logic pFET region 210. Gate stack 234comprises IL dielectric 216 c (formed from IL dielectric 216), high-Klayer 218 c (formed from high-K layer 218) over IL dielectric 216 c,metal layer 226 c (formed from metal layer 226) over a side of high-Klayer 218 c opposite IL dielectric 216 c and Si layer 228 c (formed fromSi layer 228) over a side of metal layer 226 c opposite high-K layer 218c.

Gate stack 236 is defined over SRAM pFET region 212. Gate stack 236comprises IL dielectric 216 d (formed from IL dielectric 216), high-Klayer 218 d (formed from high-K layer 218) over IL dielectric 216 d,capping layer 222 d (formed from capping layer 222) over a side ofhigh-K layer 218 d opposite IL dielectric 216 d, metal layer 226 d(formed from metal layer 226) over a side of capping layer 222 dopposite high-K layer 218 d and Si layer 228 d (formed from Si layer228) over a side of metal layer 226 d opposite capping layer 222 d.

Standard processes can then be carried out to form source and drainregions on opposite sides of the gate stacks. Oxide and/or nitridespacers can also be formed around the gate stack, as needed.

As a result of performing the steps shown illustrated in FIGS. 2A-G, anddescribed above, the capping layer will be present in gate stacks 230and 236. By including the capping layer in gate stack 230, thecorresponding logic nFET will have a V_(t) at band edge. Conversely, byexcluding the capping layer from gate stack 234, the corresponding logicpFET will also have a V_(t) at band edge. The SRAM nFET, which does nothave a capping layer in its gate stack, i.e., gate stack 232, will havea V_(t) that is about 200 mV greater than the V_(t) of the logic nFET.The SRAM pFET, which has a capping layer in its gate stack, i.e., gatestack 236, will have a V_(t) that is about 250 mV greater than the V_(t)of the logic pFET.

The above-described techniques are beneficial since they involve only asingle masking step, which is favorable for reducing production time andcosts. Other techniques, however, may be employed. For example, the samegate stack configurations can be obtained using a two-step maskingprocess. Specifically, with reference to the step shown in FIG. 2C, ametal layer, e.g., a TiN layer, rather than the capping layer, isdeposited over the high-k layer. A mask is then patterned to cover themetal layer over the SRAM nFET and logic pFET regions, allowing for theselective removal of the metal layer from over the logic nFET and SRAMpFET regions. Following the removal of the metal layer from over thelogic nFET and SRAM pFET regions, the mask is also removed.

A capping layer is then deposited over the metal layer/high-K layer,followed by a second metal layer, e.g., a second TiN layer, beingdeposited over the capping layer. A second mask is then patterned tocover the second TiN layer over the logic nFET and SRAM pFET regions,allowing for the selective removal of the second TiN and capping layersfrom over the logic pFET and SRAM nFET regions. Following the removal ofthe second TiN and capping layers from over the logic pFET and SRAM nFETregions, the mask is also removed. From this point on, the remainder ofthe process is the same as is illustrated in FIGS. 2F-G (describedabove).

FIGS. 3A-G are cross-sectional diagrams illustrating yet anotherexemplary methodology for forming an integrated SRAM-logic semiconductordevice. The device can comprise, for example, an integrated circuithaving a plurality of SRAM and logic transistors. As shown in FIG. 3A, asubstrate 304 is provided. Substrate 304 can comprise a SOI substrate ora bulk Si substrate. According to an exemplary embodiment, substrate 304comprises a SOI substrate having a Si layer over an insulator (such asSiO₂), wherein the Si layer has a thickness of between about five nm andabout 100 nm.

Substrate 304 has both SRAM and logic nFET and pFET regions definedtherein. Specifically, according to the exemplary embodiment shownillustrated in FIG. 3A, substrate 304 comprises logic nFET region 306,SRAM nFET region 308, logic pFET region 310 and SRAM pFET region 312.Each of logic nFET region 306 and SRAM nFET region 308 comprises Si andis doped with a p-type dopant. Each of logic pFET region 310 and SRAMpFET region 312 also comprises Si and is doped with an n-type dopant. Aswill be described below, cSiGe will be formed in logic pFET region 310.

A hardmask layer is deposited over the device and patterned to formhardmasks 313 and 314 over logic nFET region 306/SRAM nFET region 308and SRAM pFET region 312, respectively. With hardmask 313 shieldinglogic nFET region 306/SRAM nFET region 308 and hardmask 314 shieldingSRAM pFET region 312, cSiGe 315 is then selectively formed, i.e., grown,in logic pFET region 310. As shown in FIG. 3B, hardmasks 313 and 314 arestripped. According to an exemplary embodiment, hardmask 313 and 314 arestripped using a wet chemical etch.

As shown in FIG. 3C, IL dielectric 316 is grown over the nFET/pFETregions. According to an exemplary embodiment, IL dielectric 316comprises SiO₂. Nitrogen is then incorporated (e.g., by nitridation,thermal nitridation and/or plasma oxidation followed by nitridation)into IL dielectric 316. High-K layer 318 is then deposited over a sideof IL dielectric 316 opposite the nFET/pFET regions. According to anexemplary embodiment, high-K layer 318 comprises one or more of HfO₂,ZrO₂, HfSiO, HfSiON, Ta₂O₅, TiO₂, Al₂O₃ and mixtures comprising at leastone of the foregoing high-K materials.

Capping layer 320 is deposited over a side of high-K layer 318 oppositeIL dielectric 316. According to an exemplary embodiment, capping layer320 comprises one or more of La₂O₃, MgO, oxides of group IIA and groupIIIB elements and nitrides of group IIA and group IIIB elements.

As shown in FIG. 3D, photoresist 324 is patterned over logic nFET region306. With photoresist 324 as a mask, capping layer 320 is selectivelyremoved, i.e., stripped, from over SRAM nFET region 308, logic pFETregion 310 and SRAM pFET region 312. According to an exemplaryembodiment, capping layer 320 is selectively removed from over SRAM nFETregion 308, logic pFET region 310 and SRAM pFET region 312 using HCl.

As shown in FIG. 3E, photoresist 324 is removed, revealing the remainingportion of the capping layer formed over the logic nFET region, i.e.,capping layer 321 over logic nFET region 306. As shown in FIG. 3F, metallayer 326 is deposited over capping layer 321/high-K layer 318.According to an exemplary embodiment, metal layer 326 comprises one ormore of TiN, TaN, TaAlN, TiAlN, TaC and Ta₂C

A Si layer 328 is then deposited over a side of metal layer 326 oppositecapping layer 321/high-K layer 318. According to an exemplaryembodiment, Si layer 328 comprises poly-Si and/or amorphous Si and isdeposited to a thickness of about 1,000 Å at its thickest point.However, depending on the technology, the thickness of Si layer 328 canvary from about 500 Å to about 1,000 Å at its thickest point.

As shown in FIG. 3G, RIE is then performed through the various layers todefine individual gate stacks over each of the nFET and pFET regions.Namely, gate stack 330 is defined over logic nFET region 306. Gate stack330 comprises IL dielectric 316 a (formed from IL dielectric 316),high-K layer 318 a (formed from high-K layer 318) over IL dielectric 316a, capping layer 321 a (formed from capping layer 321) over a side ofhigh-K layer 318 a opposite IL dielectric 316 a, metal layer 326 a(formed from metal layer 326) over a side of capping layer 321 aopposite high-K layer 318 a and Si layer 328 a (formed from Si layer328) over a side of metal layer 326 a opposite capping layer 321 a.

Gate stack 332 is defined over SRAM nFET region 308. Gate stack 332comprises IL dielectric 316 b (formed from IL dielectric 316), high-Klayer 318 b (formed from high-K layer 318) over IL dielectric 316 b,metal layer 326 b (formed from metal layer 326) over a side of high-Klayer 318 b opposite IL dielectric 316 b and Si layer 328 b (formed fromSi layer 328) over a side of metal layer 326 b opposite high-K layer 318b.

Gate stack 334 is defined over logic pFET region 310. Gate stack 334comprises IL dielectric 316 c (formed from IL dielectric 316), high-Klayer 318 c (formed from high-K layer 318) over IL dielectric 316 c,metal layer 326 c (formed from metal layer 326) over a side of high-Klayer 318 c opposite IL dielectric 316 c and Si layer 328 c (formed fromSi layer 328) over a side of metal layer 326 c opposite high-K layer 318c.

Gate stack 336 is defined over SRAM pFET region 312. Gate stack 336comprises IL dielectric 316 d (formed from IL dielectric 316), high-Klayer 318 d (formed from high-K layer 318) over IL dielectric 316 d,metal layer 326 d (formed from metal layer 326) over a side of high-Klayer 318 d opposite IL dielectric 316 d and Si layer 328 d (formed fromSi layer 328) over a side of metal layer 326 d opposite high-K layer 318d.

Standard processes can then be carried out to form source and drainregions on opposite sides of the gate stacks. Oxide and/or nitridespacers can also be formed around the gate stack, as needed.

As a result of performing the steps shown illustrated in FIGS. 3A-G, anddescribed above, the capping layer will be present only in gate stack330. By including the capping layer in gate stack 330, the correspondinglogic nFET transistor will have a V_(t) at band edge. Conversely, byexcluding the capping layer from gate stack 334, the corresponding logicpFET transistor will also have a V_(t) at band edge. The SRAM nFETtransistor, which does not have a capping layer in its gate stack, i.e.,gate stack 332, will have a V_(t) that is about 200 mV greater than theV_(t) of the logic nFET transistor. The SRAM pFET transistor, which alsodoes not have a capping layer in its gate stack, i.e., gate stack 336,will have a V_(t) that is about 500 mV greater than the V_(t) of thelogic pFET transistor.

The above-described techniques are beneficial since they involve only asingle masking step, which is favorable for reducing production time andcosts. Other techniques, however, may be employed. For example, the samegate stack configurations can be obtained using a two-step maskingprocess. Specifically, with reference to the step shown in FIG. 3C, ametal layer, e.g., a TiN layer, rather than the capping layer, isdeposited over the high-k layer. A mask is then patterned to cover themetal layer over the SRAM nFET, logic pFET and SRAM pFET regions,allowing for the selective removal of the metal layer from over thelogic nFET region. Following the removal of the metal layer from overthe logic nFET region, the mask is also removed.

A capping layer is then deposited over the metal layer/high-K layer,followed by a second metal layer, e.g., a second TiN layer, beingdeposited over the capping layer. A second mask is then patterned tocover the second TiN layer over the logic nFET region, allowing for theselective removal of the second TiN and capping layers from over theSRAM nFET, logic pFET and SRAM pFET regions. Following the removal ofthe second TiN and capping layers from over the SRAM nFET, logic pFETand SRAM pFET regions, the mask is also removed. From this point on, theremainder of the process is the same as is illustrated in FIGS. 3F-G(described above).

FIGS. 4A-L are cross-sectional diagrams illustrating still yet anotherexemplary methodology for forming an integrated SRAM-logic semiconductordevice. The device can comprise, for example, an integrated circuithaving a plurality of SRAM and logic transistors. As shown in FIG. 4A, asubstrate 402 is provided. Substrate 402 can comprise a SOI substrate ora bulk Si substrate. According to an exemplary embodiment, substrate 402comprises a SOI substrate having a Si layer over an insulator (such asSiO₂), wherein the Si layer has a thickness of between about five nm andabout 100 nm. Substrate 402 has shallow trench isolation (STI) regions403, 404 and 405 defined therein. As will be described in detail below,STI regions 403, 404 and 405 will serve to divide, and thereby define,nFET and pFET regions of the device. Namely, a region of the deviceshown to the left of STI region 403 will be a logic nFET region of thedevice, and a region of the device shown to the right of STI region 403will be a SRAM pFET region of the device. A region of the device shownto the left of STI region 404 will be a SRAM nFET region of the device,and a region of the device shown to the right of STI region 404 will bea logic pFET region of the device. STI region 405 separates the SRAMpFET region of the device from the SRAM nFET region of the device.

As shown in FIG. 4B, IL dielectric 406 is grown over the nFET and pFETregions. IL dielectric 406 is separated by STI regions 403, 404 and 405.As shown in FIG. 4C, high-K layer 408 is deposited over IL dielectric406/STI region 403/STI region 404/STI region 405. According to anexemplary embodiment, high-K layer 408 comprises one or more of HfO₂,ZrO₂, HfSiO, HfSiON, Ta₂O₅, TiO₂, Al₂O₃ and mixtures comprising at leastone of the foregoing high-K materials.

A capping layer is then deposited over a side of high-K layer 408opposite IL dielectric 406/STI region 403/STI region 404/STI region 405.The capping layer can comprise one or more of La₂O₃, MgO, oxides ofgroup IIA and group IIIB elements and nitrides of group IIA and groupIIIB elements. The capping layer is then selectively removed from overthe SRAM nFET/logic pFET regions to form capping layer 410 over thelogic nFET/SRAM pFET regions, as shown in FIG. 4D. According to anexemplary embodiment, the capping layer is selectively removed from overthe SRAM nFET/logic pFET regions using HCl.

As shown in FIG. 4E, metal layer 412, is deposited over capping layer410/high-K layer 408. According to an exemplary embodiment, metal layer412 comprises one or more of TiN, TaN, TaAlN, TiAlN, TaC and Ta₂C. Asshown in FIG. 4F, a Si layer, i.e., Si layer 414, is deposited overmetal layer 412. According to an exemplary embodiment, Si layer 414comprises poly-Si or amorphous Si.

As shown in FIG. 4G, RIE is then performed through the various layers todefine individual gate stacks over each of the nFET and pFET regions.Namely, gate stack 430 is defined over the logic nFET region. Gate stack430 comprises IL dielectric 406 a (formed from IL dielectric 406),high-K layer 408 a (formed from high-K layer 408) over IL dielectric 406a, capping layer 410 a (formed from capping layer 410) over a side ofhigh-K layer 408 a opposite IL dielectric 406 a, metal layer 412 a(formed from metal layer 412) over a side of capping layer 410 aopposite high-K layer 408 a and Si layer 414 a (formed from Si layer414) over a side of metal layer 412 a opposite capping layer 410 a.

Gate stack 432 is defined over the SRAM pFET region. Gate stack 432comprises IL dielectric 406 b (formed from IL dielectric 406), high-Klayer 408 b (formed from high-K layer 408) over IL dielectric 406 b,capping layer 410 b (formed from capping layer 410) over a side ofhigh-K layer 408 b opposite IL dielectric 406 b, metal layer 412 b(formed from metal layer 412) over a side of capping layer 410 bopposite high-K layer 408 b and Si layer 414 b (formed from Si layer414) over a side of metal layer 412 b opposite capping layer 410 b.

Gate stack 434 is defined over the SRAM nFET region. Gate stack 434comprises IL dielectric 406 c (formed from IL dielectric 406), high-Klayer 408 c (formed from high-K layer 408) over IL dielectric 406 c,metal layer 412 c (formed from metal layer 412) over a side of high-Klayer 408 c opposite IL dielectric 406 c and Si layer 414 c (formed fromSi layer 414) over a side of metal layer 412 c opposite high-K layer 408c.

Gate stack 436 is defined over the logic pFET region. Gate stack 436comprises IL dielectric 406 d (formed from IL dielectric 406), high-Klayer 408 d (formed from high-K layer 408) over IL dielectric 406 d,metal layer 412 d (formed from metal layer 412) over a side of high-Klayer 408 d opposite IL dielectric 406 d and Si layer 414 d (formed fromSi layer 414) over a side of metal layer 412 d opposite high-K layer 408d.

As shown in FIG. 4H, a combination of spacers is formed adjacent to eachof the gate stacks. Namely, with regard to the logic nFET region,nitride spacers 440 a are formed adjacent to gate stack 430, oxidespacers 442 a are then formed adjacent to nitride spacers 440 a andnitride spacers 444 a are formed adjacent to oxide spacers 442 a. Withregard to the SRAM pFET region, nitride spacers 440 b are formedadjacent to gate stack 432, oxide spacers 442 b are then formed adjacentto nitride spacers 440 b and nitride spacers 444 b are formed adjacentto oxide spacers 442 b. With regard to the SRAM nFET region, nitridespacers 440 c are formed adjacent to gate stack 434, oxide spacers 442 care then formed adjacent to nitride spacers 440 c and nitride spacers444 c are formed adjacent to oxide spacers 442 c. With regard to thelogic pFET region, nitride spacers 440 d are formed adjacent to gatestack 436, oxide spacers 442 d are then formed adjacent to nitridespacers 440 d and nitride spacers 444 d are formed adjacent to oxidespacers 442 d.

Source/drain diffusions are formed in each of the nFET and pFET regions.Namely, source/drain diffusions 446 a and 448 a are formed in the logicnFET region, source/drain diffusions 446 b and 448 b are formed in theSRAM pFET region, source/drain diffusions 446 c and 448 c are formed inthe SRAM nFET region and source/drain diffusions 446 d and 448 d areformed in the logic pFET region.

Exposed Si areas in each of the nFET and pFET regions are thensilicided. As a result, silicide regions 450 a are formed in the exposedSi areas of the logic nFET region, i.e., at gate stack 430 andsource/drain diffusions 446 a and 448 a. Silicide regions 450 b areformed in the exposed Si areas of the SRAM pFET region, i.e., at gatestack 432 and source/drain diffusions 446 b and 448 b. Silicide regions450 c are formed in the exposed Si areas of the SRAM nFET region, i.e.,at gate stack 434 and source/drain diffusions 446 c and 448 c. Silicideregions 450 d are formed in the exposed Si areas of the logic pFETregion, i.e., at gate stack 436 and source/drain diffusions 446 d and448 d.

Following silicidation, the nitride spacers are removed from each of thenFET and pFET regions, as shown in FIG. 4I. As shown in FIG. 4J, atensile silicon nitride (SiN) layer is deposited over the nFET regions.Namely, SiN layer 452 is deposited over the logic nFET region and SiNlayer 454 is deposited over the SRAM nFET region. The tensile SiNlayers, in combination with a compressive SiN layer (described below),form a dual stressed liner over the device. The tensile SiN layersfurther shield the nFET regions during a subsequent oxidation process ofthe pFET regions (see below).

As shown in FIG. 4K, oxidation is used to obtain a band-edge shift inthe pFET regions. The term “band-edge shift,” as used herein, refers toneutralizing positively charged oxygen vacancies by exposing the high-Klayer, i.e., which as described above can be hafnium (Hf)-based, tooxygen (O₂) (e.g., as indicated by arrows 455). The elimination of thispositive charge provides a positive shift in the V_(t) such that theV_(t) is closer to the ideal pFET band-edge position, which isdesirable.

As shown in FIG. 4L, a compressive SiN layer is deposited over the pFETregions. Namely, SiN layer 456 is deposited over the SRAM pFET regionand SiN layer 458 is deposited over the logic pFET region. Ashighlighted above, the tensile SiN layers, in combination with thecompressive SiN layers, form a dual stressed liner over the device.

FIG. 5 is graph 500 illustrating a flat band voltage (V_(fb)) shift inan n-channel metal-oxide semiconductor capacitor (nMOSCAP) having ahigh-K/metal gate stack with a, i.e., La₂O₃, capping layer versus anMOSCAP having a high-K/metal gate stack without a capping layer. BothnMOSCAP gate stacks were exposed to a 1,000 degrees Celsius (° C.), fivesecond activation anneal. Graph 500 plots gate bias (measured in volts(V)) versus capacitance density (measured in microfarad per squarecentimeter (μF/cm²). An area A of the capacitor is 10×10 squaremicrometers (μm²).

Although illustrative embodiments of the present invention have beendescribed herein, it is to be understood that the invention is notlimited to those precise embodiments, and that various other changes andmodifications may be made by one skilled in the art without departingfrom the scope of the invention.

1. A semiconductor device comprising: a substrate having at least a first and a second nFET region, and at least a first and a second pFET region; at least one logic nFET on the substrate over the first nFET region; at least one logic pFET on the substrate over the first pFET region; at least one SRAM nFET on the substrate over the second nFET region; and at least one SRAM pFET on the substrate over the second pFET region, wherein each of the logic nFET, logic pFET, SRAM nFET and SRAM pFET comprises a gate stack having a metal layer over a high-K layer, wherein the logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, and wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.
 2. The device of claim 1, wherein the first and second nFET regions and the first and second pFET regions comprise silicon.
 3. The device of claim 1, wherein the first and second pFET regions comprise crystalline silicon germanium.
 4. The device of claim 1, wherein the first and second pFET regions comprise crystalline silicon germanium, and wherein the crystalline silicon germanium in the second pFET region is configured to have a reduced germanium fraction.
 5. The device of claim 1, wherein the first pFET region comprises crystalline silicon germanium.
 6. The device of claim 1, wherein the substrate comprises one or more of a silicon-on-insulator substrate and a bulk silicon substrate.
 7. The device of claim 1, wherein the SRAM pFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, the capping layer being configured to shift the threshold voltage of the SRAM pFET relative to the threshold voltage of one or more of the logic nFET, logic pFET and SRAM nFET.
 8. The device of claim 1, wherein the metal layer comprises one or more of titanium nitride, tantalum nitride, tantalum aluminum nitride, titanium aluminum nitride and tantalum carbide.
 9. The device of claim 1, wherein the capping layer comprises one or more of lanthanum oxide, magnesium oxide, oxides of group IIA and group IIIB elements and nitrides of group IIA and group IIIB elements.
 10. The device of claim 1, wherein the high-K layer comprises one or more of hafnium oxide, zirconium oxide, hafnium silicate, nitrided hafnium silicate, tantalum oxide, titanium oxide, aluminum oxide and mixtures comprising at least one of the foregoing high-K materials.
 11. The device of claim 1, wherein the logic nFET, logic pFET, SRAM nFET and SRAM pFET gate stacks each further comprise a silicon layer over the metal layer.
 12. The device of claim 11, wherein the silicon layer comprises one or more of polysilicon and amorphous silicon.
 13. The device of claim 1, wherein the logic nFET, logic pFET, SRAM nFET and SRAM pFET gate stacks each further comprise an interfacial layer dielectric separating the high-K layer from the substrate.
 14. The device of claim 1, wherein the substrate further comprises one or more shallow trench isolation regions present therein between at least two of the first nFET region, the second nFET region, the first pFET region and the second pFET region.
 15. The device of claim 1, wherein the logic pFET and SRAM pFET gate stack are oxidized so as to shift the threshold voltage of the logic pFET and SRAM pFET relative to a threshold voltage of one or more of the logic nFET and SRAM nFET.
 16. The device of claim 1, further comprising a tensile silicon nitride layer over one or more of the logic nFET and SRAM nFET, and a compressive silicon nitride layer over one or more of the logic pFET and SRAM pFET.
 17. An integrated circuit comprising: a substrate having at least a first and a second nFET region, and at least a first and a second pFET region; at least one logic nFET on the substrate over the first nFET region; at least one logic pFET on the substrate over the first pFET region; at least one SRAM nFET on the substrate over the second nFET region; and at least one SRAM pFET on the substrate over the second pFET region, wherein each of the logic nFET, logic pFET, SRAM nFET and SRAM pFET comprises a gate stack having a metal layer over a high-K layer, wherein the logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, and wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET. 